Rectifier circuit and semiconductor device using the same

A rectifier circuit comprising:

• a first transistor whose gate electrode is connected to a node 2, whose first electrode is connected to a node 1, and whose second electrode is connected to a second terminal;
• a second transistor whose gate electrode is connected to the node 1, whose first electrode is connected to the node 2, and whose second electrode is connected to a first terminal;
• a third transistor whose gate electrode is connected to the node 1, whose first electrode is connected to a node 3, and whose second electrode is connected to the node 1;
• a fourth transistor whose gate electrode is connected to the node 3, whose first electrode is connected to a fourth terminal, and whose second electrode is connected to the node 3;
• a first capacitor whose first electrode is connected to the first terminal and whose second electrode is connected to the node 1;
• a second capacitor whose first electrode is connected to the second terminal and whose second electrode is connected to the node 2;
• a third capacitor whose first electrode is connected to the fourth terminal and whose second electrode is grounded;
• and
• a fourth capacitor whose first electrode is connected to the node 2 and whose second electrode is connected to the node 3,
• wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are n-channel enhancement transistors, and
• wherein AC voltage input to the first terminal and the second terminal is rectified to DC voltage and the DC voltage is output to the fourth terminal.

A rectifier circuit comprising:

• a first transistor whose gate electrode is connected to a node 2, whose first electrode is connected to a node 1, and whose second electrode is connected to a second terminal;
• a second transistor whose gate electrode is connected to the node 1, whose first electrode is connected to the node 2, and whose second electrode is connected to a first terminal;
• a third transistor whose gate electrode is connected to the node 1, whose first electrode is connected to a node 3, and whose second electrode is connected to the node 1;
• a fourth transistor whose gate electrode is connected to the node 3, whose first electrode is connected to a fourth terminal, and whose second electrode is connected to the node 3;
• a fifth transistor whose gate electrode is connected to the node 3, whose first electrode is connected to the node 2, and whose second electrode is connected to the fourth terminal;
• a first capacitor whose first electrode is connected to the first terminal and whose second electrode is connected to the node 1;
• a second capacitor whose first electrode is connected to the second terminal and whose second electrode is connected to the node 2;
• a third capacitor whose first electrode is connected to the fourth terminal and whose second electrode is grounded;
• and
• a fourth capacitor whose first electrode is connected to the node 2 and whose second electrode is connected to the node 3,
• wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are n-channel enhancement transistors, and
• wherein AC voltage input to the first terminal and the second terminal is rectified to DC voltage and the DC voltage is output to the fourth terminal.