A/d conversion device
AssigneesDenso Corporation, Olympus Corporation
InventorShuichi Kato
Life of this patent
Estimating the term…
Abstract
An A/D conversion device has first to third pulse delay circuits, first to third pulse passage stage detection circuits, a time output circuit, and an output circuit. Each of the first to third pulse delay circuit has multiple stages of delay units which are connected together and delay a first to a third pulse signals, respectively. Each of the first to third pulse passage stage detection circuit detects a first to a third number of stages, respectively. The time output circuit outputs a time signal. The output circuit outputs the digital value corresponding to the third number of stages.
Claims4
An A/D conversion device which converts an analog input voltage to a digital value, the A/D conversion device comprising:
- a first pulse delay circuit which receives a first pulse signal at a first time as input, and has multiple stages of delay units which are connected together and delay the first pulse signal for a delay period according to a magnitude of a first analog voltage;
- a first pulse passage stage detection circuit which detects a first number of stages when the first pulse signal has passed through the delay unit in the first pulse delay circuit;
- a second pulse delay circuit which receives a second pulse signal at a second time that is the same as the first time, and has multiple stages of delay units which are connected together and delay the second pulse signal for a delay period according to a magnitude of a second analog voltage different from the first analog voltage;
- a second pulse passage stage detection circuit which detects a second number of stages when the second pulse signal has passed through a delay unit in the second pulse delay circuit;
- a time output circuit which outputs a time signal indicating a time at which a difference between the first number of stages and the second number of stages becomes a predetermined number of stages;
- a third pulse delay circuit which receives a third pulse signal at a third time as input, at a same time as the first time and the second time as input, and has delay units which are connected together and delay the third pulse signal for a delay period according to a magnitude of the analog input voltage;
- a third pulse passage stage detection circuit which detects a third number of stages when the third pulse signal has passed through a delay unit in the third pulse delay circuit;
- and
- an output circuit which outputs the digital value corresponding to the third number of stages detected at a time indicated by the time signal.
Dependencies are inferred from the claim text.