Zero pin serial interface

A system for controlling the performance of an integrated circuit, comprising:

• an integrated circuit;
• a first pin connected to the integrated circuit and configured to receive a mode control signal;
• a first input circuit connected to the first pin, the first input circuit configured to determine whether the integrated circuit is in an instruction reception mode or a normal operation mode based on the mode control signal;
• a second pin connected to the integrated circuit and configured to receive an instruction signal when the integrated circuit is in the instruction reception mode and transmit an output signal when the integrated circuit is in the normal operation mode;
• and
• a second input circuit connected to the second pin, the second input circuit configured to receive the instruction signal received on the second pin.

A method for receiving instructions on an integrated circuit, the method comprising:

• receiving an input voltage on a first pin, wherein the input voltage instructs the integrated circuit to receive instructions;
• dividing the input voltage with a voltage divider;
• comparing the divided voltage against a bandgap voltage to determine whether the divided voltage is less than the bandgap voltage;
• when the divided voltage is less than the bandgap voltage, directing the integrated circuit to enter an instruction reception mode;
• identifying a first voltage level and a second voltage level by dividing the input voltage using a series of voltage dividers;
• receiving a control signal on a second pin;
• deriving a data portion by comparing the control signal with the first voltage level;
• deriving a clock portion by comparing the control signal with the second voltage level;
• delaying the clock portion by a predetermined amount of time;
• using the clock portion for synchronizing with the performance adjusting instruction;
• and
• processing the data portion.

A method for setting the output voltage of a voltage reference device after packaging, the method comprising:

• identifying a desired output voltage for the voltage reference device;
• transmitting a first change mode signal to the voltage reference device on a first pin, wherein the first change mode signal is processed by a first input circuit, the first input circuit directing the voltage reference device to enter an instruction reception mode, wherein the first pin receives an input voltage during a voltage output mode;
• transmitting a performance adjusting instruction to the voltage reference device on a second pin, wherein the performance adjusting instruction is processed by a second input circuit, the second input circuit acquiring command data and synchronization information from the performance adjusting instruction, wherein the second pin outputs a voltage reference during the voltage output mode;
• transmitting a second change mode signal to the voltage reference device on the first pin, wherein the second change mode signal causes the voltage reference device to enter the voltage output mode;
• comparing an output voltage of the voltage reference device to the desired output voltage of the voltage reference device, wherein the output voltage is the voltage reference output from the second pin during the voltage output mode;
• and
• setting the voltage reference device to permanently transmit the output voltage from the second pin when the output voltage is within a desired tolerance of the desired output voltage.

A system for post package trimming a device, the system comprising:

• a packaged integrated circuit having a plurality of pins, wherein each pin in the plurality of pins has a functional purpose when the packaged integrated circuit operates in a normal operation mode, the packaged integrated circuit comprising:
• a first input circuit connected to a first pin in the plurality of pins, the first input circuit configured to determine whether the packaged integrated circuit is in an instruction reception mode or a normal operation mode based on a mode control signal received on the first pin;
• and
• a second input circuit connected to a second pin in the plurality of pins, the second input circuit configured to receive commands on the second pin;
• at least one memory device configured to store a plurality of commands for transmission to the packaged integrated circuit;
• and
• a processing unit configured to control the mode control signal and transmit the mode control signal to the first pin, the processing unit also configured to transmit the commands to the second pin, wherein the processing unit compares the performance of the packaged integrated circuit and transmits commands to the packaged integrated circuit until the performance of the packaged integrated circuit is within a desired tolerance.

A system for converting a signal:

• an input signal source configured to provide an input signal, wherein the input signal is in a first format;
• a signal converter configured to convert the input signal into an output signal, wherein the output signal is in a second format;
• a output signal application configured to receive the output signal from the signal converter;
• a voltage reference comprising:
• a first input circuit configured to determine whether the voltage reference is in an instruction reception mode or a normal operation mode based on a received mode control signal;
• an output pin configured to receive an instruction signal when the voltage reference is in the instruction reception mode and transmit a reference voltage to the signal converter when the voltage reference is in the normal operation mode;
• and
• a second input circuit configured to derive data and synchronization information from the instruction signal received on the second pin when the voltage reference is in the instruction reception mode;
• and
• a power supply configured to provide a mode control signal to the voltage reference on the first pin such that the voltage reference remains in normal operation mode.