Phase-locked loop based frequency synthesizer and method of operating the same
AssigneeKorea Electronics Technology Institute
InventorsKi-Jin Kim, Kwang Ho Ahn
Life of this patent
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Abstract
A phase-locked loop based frequency synthesizer generates a plurality of output reference signals by phase-delaying an input reference signal and generates a plurality of comparison signals by using a signal having a frequency divided by the fractional frequency divider. Here, the comparison signals are lower than the divided frequency. Further, the phase-locked loop based frequency synthesizer controls an output frequency of a voltage controlled oscillator through phase and frequency comparison between the plurality of output reference signals and the plurality of comparison signals.
Claims8
A phase-locked loop based frequency synthesizer comprising:
- a voltage controlled oscillator for controlling an output frequency by a control voltage;
- a multi-signal generator that uses an input reference signal to generate a plurality of output reference signals having the same frequency as and a different phase from that of the input reference signal by the input reference signal;
- a fractional frequency divider for dividing the output frequency and outputting the same;
- a pulse generator that uses a signal having a frequency divided by the fractional frequency divider to generate a plurality of comparison signals each having a comparison frequency lower than the divided frequency;
- a plurality of phase frequency detectors for outputting a pulse signal according to differences in phase and frequency between the plurality of output reference signals and the comparison signals;
- a plurality of charge pumps for generating a control current corresponding to the pulse signal of the phase frequency detectors;
- and
- a loop filter for generating the control voltage from the control current generated by the plurality of charge pumps and outputting the same to the voltage controlled oscillator.
A method of operating a phase-locked loop based frequency synthesizer, the method comprising:
- generating m output reference signals obtained by dividing one period of an input reference signal by m phases;
- fractionally dividing an output frequency of a voltage controlled oscillator according to the control of a sigma-delta modulator;
- separating a signal having the fractionally divided frequency into m comparison signals;
- generating m pulse signals according to the comparison in phase and frequency between the m output reference signals and the m comparison signals;
- generating a control voltage by the m pulse signals;
- and
- controlling the output frequency by the control voltage.
Dependencies are inferred from the claim text.