Method and apparatus for correcting phase offset errors in a communication device

A delay locked loop for a frequency synthesizer, comprising:

• a phase detector having first and second ports for receiving either a reference clock frequency or a DLL frequency output signal through first and second multiplexed input ports;
• a charge pump coupled to the phase detector, the charge pump generating a delay line voltage control signal;
• a voltage controlled delay line coupled to the charge pump, the voltage controlled delay line receiving the reference frequency and the delay line voltage control signal and generating the DLL frequency output signal;
• a loop filter capacitor coupled to the voltage control delay line;
• an auto-tuning circuit for receiving the reference frequency signal, a voltage reference signal and the delay line voltage control signal, the auto-tuning circuit generating a correction signal to minimize static error in the voltage control line.

A frequency synthesizer, comprising:

• a phase-lock loop (PLL) having a wide bandwidth loop and a narrow bandwidth loop;
• a wideband charge-pump for generating a wide loop bandwidth signal within the wide bandwidth loop during adapt-mode operation;
• a narrowband charge-pump for generating a narrow loop bandwidth signal within the narrow bandwidth loop during normal-mode operation;
• a comparator for comparing the wideband charge-pump output with a reference value and generating a comparator output indicative of static phase offset error;
• a phase offset correction current applied to the wideband charge-pump;
• and
• an auto-tune circuit for adjusting the comparator value for phase lock mismatch minimization/elimination and generating a correction value, the correction value being applied to the phase offset correction current thereby minimizing transients and settling time when switching between the wideband loop to the narrowband loop.

A method for auto-tuning a synthesizer having a phase detector and a charge pump, comprising:

• measuring static phase error at an output signal;
• integrating the static phase error in the synthesizer;
• generating a correction value based on the integrated static phase error using a feedback control algorithm;
• and applying the correction value to a synthesizer control signal.