Fractional-N PLL Using Multiple Phase Comparison Frequencies to Improve Spurious Signal Performance

An apparatus including phase-locked loop (PLL) circuitry, comprising:

• programmable comparison signal generator means for receiving one or more reference control signals and a reference signal having a reference frequency Fref and in response thereto providing a comparison signal having a programmable comparison frequency Fpd;
• phase detector means for receiving said comparison signal and a feedback signal and in response thereto providing a phase detection signal;
• controllable oscillator means for receiving said phase detection signal and in response thereto providing a PLL output signal having one Fch of a plurality of output frequencies each of which is equal to a multiple of said comparison frequency;
• and
• programmable feedback frequency divider means for receiving said PLL output signal and one or more feedback control signals and in response thereto providing said feedback signal;
• wherein
• said plurality of output frequencies is bounded by minimum Fl and maximum Fh output frequencies in relation to said one or more feedback control signals,
• a predetermined minimum offset frequency Fos—min is defined in relation to a difference between each of said plurality of output frequencies and a respective one of a plurality of primary fractional spurious signal frequencies, and
• said reference frequency is greater than or equal to a sum of
• a difference Fh−Fl between said maximum and minimum output frequencies, and double said minimum offset frequency 2Fos—min.

A method for providing a phase-locked signal, comprising:

• receiving one or more reference control signals and a reference signal having a reference frequency Fref and in response thereto providing a comparison signal having a programmable comparison frequency Fpd;
• receiving said comparison signal and a feedback signal and in response thereto providing a phase detection signal;
• receiving said phase detection signal and in response thereto providing a PLL output signal having one Fch of a plurality of output frequencies each of which is equal to a multiple of said comparison frequency;
• and
• receiving said PLL output signal and one or more feedback control signals and in response thereto providing said feedback signal;
• wherein
• said plurality of output frequencies is bounded by minimum Fl and maximum Fh output frequencies in relation to said one or more feedback control signals,
• a predetermined minimum offset frequency Fos—min is defined in relation to a difference between each of said plurality of output frequencies and a respective one of a plurality of primary fractional spurious signal frequencies, and
• said reference frequency is greater than or equal to a sum of
• a difference Fh−Fl between said maximum and minimum output frequencies, and double said minimum offset frequency 2Fos—min.