System and method for open loop modulation to detect narrow pwm pulse

A gate driver with open loop modulation for a voltage regulator with an output phase node, said gate driver comprising:

• an upper gate driver which receives an output control signal and an upper deadtime control signal and which provides an upper gate drive signal;
• a lower gate driver which receives said output control signal and a lower deadtime control signal and which provides a lower gate drive signal;
• a deadtime controller having inputs receiving said upper and lower gate driver signals and outputs providing said upper and lower deadtime control signals, wherein said deadtime controller asserts said upper deadtime control signal after said lower gate drive signal is detected negated, and wherein said deadtime controller asserts said lower deadtime control signal when said upper gate drive signal is detected negated;
• and
• an open loop modulation network, comprising:
• a latch network which latches assertion of a pulse control signal and which provides a corresponding latched control pulse indication;
• an output sense network which detects initiation of an output pulse on the output phase node and which provides a corresponding output pulse indication;
• a timing network which initiates a delay period in response to at least one of said output pulse indication and deassertion of said pulse control signal, and which resets said latched control pulse indication after expiration of said delay period;
• and
• a pulse control network which controls said output control signal to initiate said output pulse, and to terminate said output pulse after reset of said latched control pulse indication and deassertion of said pulse control signal have both occurred.

A gate driver with open loop modulation for a voltage regulator with an output phase node, said gate driver comprising:

• a latch network which latches assertion of a pulse control signal;
• a lower gate driver coupled to said latch network which negates a lower gate drive signal after assertion of said pulse control signal is latched;
• a minimum pulse generator which generates a minimum pulse signal when an output pulse is detected on the phase node;
• and
• an upper gate driver coupled to said latch network which asserts an upper gate drive signal after said pulse control signal is latched and said lower gate drive signal is detected negated, and which negates said upper gate drive signal after both said minimum pulse signal is completed and said pulse control signal is negated.

A method of open loop modulation for a driver of a voltage regulator, comprising:

• latching assertion of a pulse control signal and providing a latched pulse control signal;
• providing the latched pulse control signal to the driver to initiate an output pulse;
• detecting assertion of the output pulse and providing an output pulse indication;
• initiating a delay period after at least one of receiving the output pulse indication and deassertion of the pulse control signal;
• and
• terminating the output pulse after the last to occur between expiration of the delay period and deassertion of the pulse control signal.