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US 2012/0074571 A1Published application
Methods and architectures for bottomless interconnect vias
AssigneeIntel Corporation
InventorAdrien R. Lavoie
Life of this patent
Estimating the term…
Abstract
An apparatus includes an interconnect in a recess. The interconnect includes a liner structure and the liner structure in the recess. The liner structure is breached at the recess bottom feature and a bottom interconnect makes a single-interface contact with a subsequent interconnect through the breach.
Claims16
A process comprising:
- forming a recess in a dielectric layer, wherein the dielectric layer is disposed above and on a first interconnect, wherein the recess includes a feature wall and a feature bottom, and wherein forming the recess exposes at least a portion the first interconnect at the feature bottom;
- and
- forming a liner structure in the recess under conditions to remove the liner structure from the feature bottom and to expose the first interconnect at an upper surface thereof, and wherein forming the liner structure includes:
- forming a barrier first layer in the recess to cover the feature wall and the feature bottom;
- forming a liner second layer in the recess to cover the barrier first layer;
- applying a radio frequency (RF) bias under conditions to remove the barrier first layer and the liner second layer from the feature bottom;
- forming a seed third layer in the recess to cover the liner second layer and the feature bottom;
- and
- applying an RF bias under conditions to remove the seed layer from the feature bottom and to expose the first interconnect at an upper surface thereof.
6 more elements
3-6. (canceled)
9-10. (canceled)
A process comprising:
- forming a recess in a dielectric layer, wherein the dielectric layer is disposed above and on a first interconnect, wherein the recess includes a feature wall and a feature bottom, and wherein forming the recess exposes at least a portion the first interconnect at the feature bottom;
- and
- forming a liner structure in the recess under conditions to remove the liner structure from the feature bottom and to expose the first interconnect at an upper surface thereof, wherein forming the liner structure includes:
- forming a barrier first layer in the recess to cover the feature wall and the feature bottom;
- forming a liner second layer in the recess to cover the barrier first layer;
- forming a seed third layer in the recess to cover the adhesion second film and under conditions to breach the barrier first film, the adhesion second film, and the seed third film and to expose the first interconnect at the feature floor, and wherein the conditions include a direct-current (DC) and an RF first-bias physical vapor deposition and an RF second-bias resputter process;
- filling the recess upon the seed third layer with a second interconnect, material under conditions to form a single resistance interface between the first interconnect and the second interconnect material;
- and
- planarizing the second interconnect material to form a second interconnect.
6 more elements
A process comprising:
- forming a recess in a dielectric layer, wherein the dielectric layer is disposed above and on a first interconnect, wherein the recess includes a feature wall and a feature bottom and wherein forming the recess exposes at least a portion the first interconnect at the feature bottom;
- and
- forming a liner structure in the recess under conditions to remove the liner structure from the feature bottom and to expose the first interconnect at an upper surface thereof, wherein the conditions to remove the liner structure from the feature bottom and to expose the first:
- interconnect at an upper surface thereof includes carrying out at least one pulsed RF re-deposition process on the liner structure.
1 more element
-24. (canceled)
A process comprising:
- forming a recess in a dielectric layer, wherein the dielectric layer is disposed above and on a first interconnect, wherein the recess includes a feature wall and a feature bottom, and wherein forming the recess exposes at least a portion the first interconnect at the feature bottom;
- and
- forming a liner structure in the recess under conditions to remove the liner structure from the feature bottom and to expose the first interconnect at an upper surface thereof, wherein forming the liner structure includes sputtering the liner structure with a pulsed radio frequency (RE) bias to expose the first interconnect.
28-32. (canceled)
A process comprising:
- forming a recess in a dielectric layer, wherein the dielectric layer is disposed above and on a first interconnect, wherein the recess includes a feature wall and a feature bottom, and wherein forming the recess exposes at least a portion the first interconnect at the feature bottom;
- and
- forming a liner structure in the recess under conditions to remove the liner structure from the feature bottom and to expose the first interconnect at an upper surface thereof, wherein forming the liner structure includes sputtering the liner structure with a pulsed radio frequency (RF) bias to expose the first interconnect.
A process comprising:
- forming a recess in a dielectric layer, wherein the dielectric layer is disposed above and on a first interconnect, wherein the recess includes a feature wall and a feature bottom, and wherein forming the recess exposes at least a portion the first interconnect at the feature bottom;
- and
- forming a liner structure in the recess under conditions to remove the liner structure from the feature bottom and to expose the first interconnect at an upper surface thereof, wherein forming the liner structure includes sputtering the liner structure with a pulsed radio frequency (RF) bias to expose the first interconnect, wherein to expose the first interconnect at the upper surface thereof, one is used of increasing the RF bias, holding the RF bias constant, and decreasing the RF bias.
35-38. (canceled)
Dependencies are inferred from the claim text.