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US 2012/0074492 A1Published application
Method of Fabricating A Semicoductor Device Having A Lateral Double Diffused Mosfet Transistor with a Lightly Doped Source and a CMOS Transistor
AssigneeVolterra Semiconductor Corporation
InventorsBudong Yu, Marco A. Zuniga
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Abstract
Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described.
Claims27
A device comprising:
- a laterally diffused metal oxide semiconductor (LDMOS) transistor on a substrate, the LDMOS transistor including a first drain with a first drain-side n+ region, a first source with a first source-side n+ region and a first source-side p+ region, a first gate between the first drain and the first source, and a first lightly n-doped region in the first source that overlaps the first source-side n+ region and extends beneath the first gate but not the first drain;
- and
- an n-type complementary metal oxide semiconductor (CMOS) transistor on the substrate, the n-type CMOS transistor including a second drain having a second drain-side n+ region, a second source having a second source-side n+ region, a second gate between the second drain and the second source, and a second lightly n-doped region in the second drain that overlaps the second drain-side n+ region and extends beneath the second gate.
A method of fabricating a semiconductor device, the method comprising:
- forming a n-well in a surface area of a substrate;
- forming a source including implanting a p-body in the n-well, a p+ region within the p-body, a first n+ region within the p-body and abutting the p+ region, the first n+ region on a side of the p+ region closer to a gate, and a lightly doped region that overlaps at least a portion of the first n+ region, the lightly doped region implanted only in the source;
- forming a drain including forming a second n+ region in the drain;
- and
- forming the gate between the source and the drain including forming the gate above a portion of the lightly doped region such that the lightly doped region extends laterally beneath a portion of the gate.
2 more elements
A method of fabricating a semiconductor device, the method comprising:
- implanting, into a surface of the substrate, a high voltage n-doped n-well;
- forming a gate oxide in a gate region;
- covering the gate oxide with a conductive material;
- implanting, into a source region, a p-doped p-body;
- implanting, only into the source region, a n-doped lightly doped source;
- implanting, into the source region, a first n-doped n+ region, the first n-doped n+ region overlapping a portion of the n-doped lightly doped source;
- implanting, into a drain region, a second n-doped n+ region;
- and
- implanting, into the source region, a p-doped p+ region.
6 more elements
Dependencies are inferred from the claim text.