Power semiconductor device

A power semiconductor device comprising:

• a first semiconductor layer of a first conductivity type having a first surface;
• a first pillar region provided on the first surface of the first semiconductor layer and composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately and repeatedly arranged along a first direction parallel to the first surface;
• a second pillar region provided on the first surface of the first semiconductor layer, being adjacent to the second pillar layer of the first pillar region along the first direction, and composed of:
• a pillar set composed of at least one third pillar layer of the second conductivity type and one fourth pillar layer of the first conductivity type adjacent to the third pillar layer along the first direction;
• and
• a fifth pillar layer of the second conductivity type adjacent to the pillar set along the first direction;
• an epitaxial layer of the first conductivity type provided on the first surface of the first semiconductor layer, being adjacent to the second pillar region along the first direction, and having a lower first conductivity type impurity concentration than the second pillar layer;
• a plurality of first base layers of the second conductivity type electrically connected, respectively, onto the plurality of first pillar layers and spaced from each other;
• a plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other;
• a third base layer of the second conductivity type provided on a surface of the epitaxial layer so as to be adjacently spaced from a second base layer of the plurality of second base layers, the second base layer connected onto the fifth pillar layer;
• a plurality of source layers of the first conductivity type selectively formed in respective surfaces of the plurality of first base layers and having a higher first conductivity type impurity concentration than the epitaxial layer;
• a first gate electrode provided via a first gate insulating film on adjacent ones of the plurality of first base layers, on the source layers formed on the adjacent first base layers, and on the second pillar layer;
• a second gate electrode provided via a second gate insulating film on adjacent ones of the plurality of second base layers and on the fourth pillar layer;
• a third gate electrode provided via a third gate insulating film on the third base layer and the second base layer connected onto the fifth pillar layer;
• a first electrode provided on and electrically connected to a surface of the first semiconductor layer opposite to the first surface;
• and
• a second electrode electrically connected to the source layers, the first base layers, the second base layers, and the third base layer.