Vertical transistor with hardening implatation

A method comprising:

• providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer, each pillar structure forming a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface;
• implanting a hardening species into the vertical pillar transistor top surface;
• oxidizing the vertical pillar transistor forming a top surfaces oxide material layer and a side surface oxide material layer, wherein the top surfaces oxide material layer is different than the side surface oxide material layer;
• and
• removing selectively the side surface oxide material layer to form vertical pillar transistor having rounded side surfaces and the top surfaces oxide material layer.

A method comprising:

• providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer, each pillar structure forming a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface, the vertical pillar transistor having a drain, source and channel regions vertically stacked on top of each other and extending away from the semiconductor wafer;
• implanting a hardening species into the vertical pillar transistor top surface and not into the vertical pillar transistor side surface;
• oxidizing the vertical pillar transistor forming a top surfaces oxide material layer and a side surface oxide material layer, wherein the top surfaces oxide material layer is different than the side surface oxide material layer;
• removing selectively the side surface oxide material layer to form vertical pillar transistor having rounded side surfaces and the top surfaces oxide material layer;
• and
• electrically coupling a memory cell with the vertical pillar transistor.

An apparatus comprising:

• a vertical pillar transistor extending orthogonally from a semiconductor wafer, the vertical pillar transistor comprising a planar top surface and rounded side surfaces, the rounded side surfaces are orthogonal to the planar top surface, wherein the top surface includes a hardening implant species;
• an electrically conductive gate material layer on the rounded side surfaces;
• and
• a memory cell in electrical connection with the vertical pillar transistor.