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US 2012/0074477 A1Published application
Semiconductor device having raised source and drain of differing heights
AssigneeElpida Memory, Inc.
InventorKeizo KAWAKITA
Life of this patent
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Abstract
This semiconductor device has an MOS transistor equipped with a gate electrode formed on a semiconductor substrate, a source region next to one side of the gate electrode, and a drain region next to another side of the gate electrode, wherein an upper end of the source region and an upper end of the drain region are at positions where are higher than a top surface of the semiconductor substrate, and the height of the upper end of the drain region differs from the height of the upper end of the source region.
Claims20
A semiconductor device comprising:
- a substrate;
- an isolation region selectively formed in the substrate to define an active region;
- a gate electrode passing over the active region;
- a first region formed in the active region with a first peripheral edge defined by the isolation region and a second peripheral edge defined by the gate electrode, the first region having an upper surface;
- a first silicon layer formed on the upper surface of the first region;
- a dummy gate electrode passing over the active region;
- a second region formed in the active region with a third peripheral edge defined by the isolation region, a fourth peripheral edge defined by the gate electrode and a fifth peripheral edge defined by the dummy gate electrode, the second region having an upper surface that is different in area from the upper surface of the first region;
- and
- a second silicon layer formed on the upper surface of the second region, the second silicon layer being different in thickness from the first silicon layer.
6 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- an isolation region selectively formed in the semiconductor substrate to define an active region, the active region having an upper surface;
- first and second gate lines each crossing over the active region to divide the upper surface of the active region into first, second and third surface portions, the first surface portion being between the first and second gate lines, the second surface portion being between the first gate line and the isolation region, and the third surface portion being between the second gate line and the isolation region;
- a third gate line crossing over a part of the second surface portion so that a remaining portion of the second surface portion between the first and third gate lines is smaller in width than the first surface portion;
- and
- first and second silicon layers formed on the first surface portion and the remaining portion of the second surface portion, respectively, the first and second silicon layers being different in thickness from each other.
3 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- an isolation region selectively formed in the semiconductor substrate to define an active region, the active region including first, second and third surface portions arranged in line in a first direction, the first surface portion being between the isolation region and the second surface region, and the second surface region being between the first and third surface portions;
- a first gate structure elongated in a second direction, that intersects the first direction, to cross over the second surface portion of the active region;
- a second gate structure elongated in the second direction to cross over a part of the first surface portion of the active region, the second gate structure expanding in the first direction to cover a part of the isolation region, a remaining part of the first surface portion being defined between the first and second gate structures, the remaining part of the first surface portion being smaller in width than the third surface portion;
- a first silicon layer formed in contact with the remaining part of the first surface portion of the active region;
- and
- a second silicon layer formed in contact with the third surface portion of the active region, the second silicon layer being different in thickness from the first silicon layer.
4 more elements
Dependencies are inferred from the claim text.