Metal gate structure of a semiconductor device

A method of fabricating a metal gate structure over a substrate comprising a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions, the method comprising:

• forming a first opening in a dielectric layer over the first active region, the first opening extending over at least ⅔ of the first width of the isolation region;
• partially filling the first opening with a P-work-function metal layer;
• forming a second opening adjoining the first opening in the dielectric layer over the second active region, the second opening extending over no more than ⅓ of the first width of the isolation region;
• depositing an N-work-function metal layer in the first and second openings, whereby the N-work-function metal layer is over the P-work-function metal layer in the first opening;
• depositing a signal metal layer over the N-work-function metal layer in the first and second openings;
• and
• planarizing the signal metal layer.