Asymmetric wedge jfet, related method and design structure

A method of forming a junction field effect transistor (JFET), the method comprising:

• forming a trench in the substrate, the trench having a substantially horizontal bottom surface, a substantially vertical first side and a substantially vertical second side;
• forming a quasi-buried upper gate below the trench;
• filling the trench with an insulator material to create a shallow trench isolation (STI) region, wherein the quasi-buried upper gate is disposed under a portion of the STI region such that the quasi-buried upper gate does not extend along a portion of the STI region proximate to the second side of the trench;
• forming a lower gate region below the STI region;
• forming a channel region disposed between the lower gate and the STI region;
• forming a source region adjacent to the first side of the trench;
• and
• forming a drain region adjacent to the second side of the trench.

A final design structure instantiated in a machine readable medium for designing and manufacturing a circuit, the final design structure comprising machine readable instructions for manufacturing at least one circuit and an integrated circuit, the circuit comprising:

• a junction field effect transistor (JFET) including:
• a source region having an upper surface substantially coplanar with the upper surface of the JFET, the upper surface of the source region having an inner edge and an outer edge;
• a drain region having an upper surface substantially coplanar with the upper surface of the JFET, the upper surface of the drain region having an inner edge and an outer edge;
• a channel region disposed under the source region and the drain region;
• and
• a shallow trench isolation (STI) region comprising an insulator material, the STI region having an upper surface substantially coplanar with the upper surface of the JFET, the STI region extending from the inner edge of the source region to the inner edge of the drain region.