3d memory array with vertical transistor

A method of forming a memory array comprising:

• forming a first memory array layer on a base circuitry layer, the first memory array layer is electrically coupled to the base circuitry layer, wherein the first memory array layer comprises a plurality of memory units, each memory unit comprising a vertical pillar transistor electrically coupled to a memory cell;
• disposing a semiconductor layer on the first memory array layer;
• forming a second memory array layer from the semiconductor layer;
• the second memory array layer is electrically coupled to the base circuitry layer, wherein the second memory array layer comprises a plurality of memory units, each memory unit comprising a vertical pillar transistor electrically coupled to a memory cell.