US 2012/0074418 A1 · SEMICONDUCTOR DEVICE

Abstract

NTFT of the present invention has a channel forming region, n-type first, second, and third impurity regions in a semiconductor layer. The second impurity region is a low concentration impurity region that overlaps a tapered potion of a gate electrode with a gate insulating film interposed therebetween, and the impurity concentration of the second impurity region increases gradually from the channel forming region to the first impurity region. And, the third impurity region is a low concentration impurity region that does not overlap the gate electrode. Moreover, a plurality of NTFTs on the same substrate have different second impurity region lengths, respectively, according to difference of the operating voltages. That is, when the operating voltage of the second TFT is higher than the operating voltage of the first TFT, the length of the second impurity region is longer on the second TFT than on the first TFT.

Claims16

Dependent claims

A semiconductor device comprising:

(a) a first transistor comprising:
a first semiconductor layer on an insulating layer;
a first gate insulating film over the first semiconductor layer;
and
a first gate electrode over the first semiconductor layer with the first gate insulating film interposed therebetween, the first gate electrode comprising a first conductive layer and a second conductive layer,
wherein the first transistor is an n-channel transistor, and
wherein the first conductive layer extends beyond side edges of the second conductive layer, and
(b) a second transistor comprising:
a second semiconductor layer on the insulating layer;
a second gate insulating film over the second semiconductor layer, and a second gate electrode over the second semiconductor layer with the second gate insulating film interposed therebetween, the second gate electrode comprising a third conductive layer and a fourth conductive layer,
wherein the second transistor is a p-channel transistor, and
wherein side edges of the third conductive layer are coextensive with side edges of the fourth conductive layer.

9 more elements

A semiconductor device comprising:

(a) a first transistor comprising:
a first semiconductor layer on an insulating layer;
a first gate insulating film over the first semiconductor layer;
and
a first gate electrode over the first semiconductor layer with the first gate insulating film interposed therebetween, the first gate electrode comprising a first conductive layer and a second conductive layer,
wherein the first transistor is an n-channel transistor, and
wherein the first conductive layer extends beyond side edges of the second conductive layer,
(b) a second transistor comprising:
a second semiconductor layer on the insulating layer;
a second gate insulating film over the second semiconductor layer, and
a second gate electrode over the second semiconductor layer with the second gate insulating film interposed therebetween, the second gate electrode comprising a third conductive layer and a fourth conductive layer,
wherein the second transistor is a p-channel transistor, and
(c) a silicon nitride film covering the first transistor and the second transistor, the silicon nitride film being in contact with upper surfaces of the first gate electrode and the second gate electrode,
wherein side edges of the third conductive layer are coextensive with side edges of the fourth conductive layer.

11 more elements

Dependencies are inferred from the claim text.

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims16