Semiconductor device and method for manufacturing the same

A method for manufacturing a semiconductor device, comprising the steps of:

• forming a first transistor including a first channel formation region, a first gate insulating layer provided over the first channel formation region, a first gate electrode overlapping with the first channel formation region over the first gate insulating layer, a first source electrode layer electrically connected to the first channel formation region, and a first drain electrode electrically connected to the first channel formation region;
• forming an insulating layer over the first transistor;
• planarizing the insulating layer so that a surface of the insulating layer has a root-mean-square surface roughness of less than or equal to 1 nm;
• and
• forming a second transistor including a second channel formation region including an oxide semiconductor, a second source electrode electrically connected to the second channel formation region, a second drain electrode electrically connected to the second channel formation region, a second gate electrode overlapping with the second channel formation region, and a gate insulating layer provided between the second channel formation region and the second gate electrode,
• wherein the channel formation region including the oxide semiconductor is in contact with the insulating layer, and
• wherein the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region.

A method for manufacturing a semiconductor device, comprising the steps of:

• forming a first transistor including a first channel formation region, a first gate insulating layer provided over the first channel formation region, a first gate electrode which overlaps with the first channel formation region and is provided over the first gate insulating layer, a first source electrode electrically connected to the first channel formation region, and a first drain electrode electrically connected to the first channel formation region;
• forming an insulating layer over the first transistor;
• planarizing the insulating layer so that a surface of the insulating layer has a root-mean-square roughness of less than or equal to 1 nm and a top surface of the first gate electrode is exposed to be included in a same surface as the insulating layer;
• and
• forming a second transistor including a second channel formation region including an oxide semiconductor over the insulating layer, a second source electrode electrically connected to the second channel formation region, a second drain electrode electrically connected to the second channel formation region, a second gate electrode provided to overlap with the second channel formation region, a second gate insulating layer provided between the second channel formation region and the second gate electrode,
• wherein the second source electrode or the second drain electrode are provided to be in contact with the top surface of the first gate electrode, and
• wherein the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region.

A method for manufacturing a semiconductor device, comprising the steps of:

• forming a first transistor including a first channel formation region, a first gate insulating layer provided over the first channel formation region, a first gate electrode overlapping with the first channel formation region over the first gate insulating layer, a first source electrode layer electrically connected to the first channel formation region, and a first drain electrode electrically connected to the first channel formation region;
• forming an insulating layer over the first transistor;
• planarizing the insulating layer by a CMP treatment;
• and
• forming a second transistor including a second channel formation region including an oxide semiconductor, a second source electrode electrically connected to the second channel formation region, a second drain electrode electrically connected to the second channel formation region, a second gate electrode overlapping with the second channel formation region, and a gate insulating layer provided between the second channel formation region and the second gate electrode,
• wherein the channel formation region including the oxide semiconductor is in contact with the insulating layer,
• wherein the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region.

A method for manufacturing a semiconductor device, comprising the steps of:

• forming a first transistor including a first channel formation region, a first gate insulating layer provided over the first channel formation region, a first gate electrode which overlaps with the first channel formation region and is provided over the first gate insulating layer, a first source electrode electrically connected to the first channel formation region, and a first drain electrode electrically connected to the first channel formation region;
• forming an insulating layer over the first transistor;
• planarizing the insulating layer by a CMP treatment so that a top surface of the first gate electrode is exposed to be included in a same surface as the insulating layer;
• and
• forming a second transistor including a second channel formation region including an oxide semiconductor over the insulating layer, a second source electrode electrically connected to the second channel formation region, a second drain electrode electrically connected to the second channel formation region, a second gate electrode provided to overlap with the second channel formation region, a second gate insulating layer provided between the second channel formation region and the second gate electrode,
• wherein the second source electrode or the second drain electrode are provided to be in contact with the top surface of the first gate electrode, and
• wherein the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region.