Method for copper hillock reduction

A method of forming interconnects in integrated circuits, comprising:

• providing a semiconductor substrate having one or more devices providing thereon;
• forming a copper interconnect structure, the copper interconnect structure being formed overlying a barrier layer within a thickness of an interlayer dielectric layer, the copper interconnect structure comprising a first stress characteristic;
• loading the semiconductor substrate including the copper interconnect structure into a deposition chamber;
• providing an inert environment within the deposition chamber;
• subjecting the semiconductor substrate including the copper interconnect structure to an anneal process in the inert environment for a period of time to cause the copper interconnect structure to have a second stress characteristic, the anneal process being characterized by a pressure and a temperature;
• maintaining the semiconductor substrate in the deposition chamber;
• depositing a dielectric layer overlying the copper interconnect structure, the dielectric layer being an etch stop layer;
• and
• depositing an inter-metal dielectric layer overlying the dielectric layer,
• wherein the anneal process reduces copper hillock defects resulting from at least the first stress characteristic.