Power transistor device with electrostatic discharge protection and low dropout regulator using same
AssigneeRichtek Technology Corporation
InventorJian-Hsing LEE
Life of this patent
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Abstract
The present invention discloses a power transistor device and a low dropout regulator (LDO) with electrostatic discharge protection. The power transistor device includes: a P-type metal oxide semiconductor (PMOS) field effect transistor (FET), having a source and a drain electrically connected to a voltage input terminal and a voltage output terminal respectively; and an electrostatic discharge protection device, electrically connected to the voltage input terminal and the voltage output terminal, for providing an electrostatic discharge path to protect the PMOSFET.
Claims10
A power transistor device with electrostatic discharge protection, comprising:
- a P-type metal oxide semiconductor (PMOS) field effect transistor (FET) having a source and a drain electrically connected to a voltage input terminal and a voltage output terminal, respectively;
- and
- an electrostatic discharge protection device electrically connected to the voltage input terminal and the voltage output terminal, for providing an electrostatic discharge path such that the electrostatic voltage at the voltage output terminal discharges through the electrostatic discharge path, to protect the PMOSFET,
- wherein the voltage output terminal includes a contact pad for providing an electrical connection to a load circuit.
A low dropout (LDO) regulator with electrostatic discharge protection, for converting an input voltage at a voltage input terminal to an output voltage at a voltage output terminal, the LDO regulator comprising:
- an error amplifier circuit generating an error amplified signal according to an output voltage sampled signal and a reference signal, wherein the output voltage sampled signal is sampled from the output voltage;
- and
- a power transistor device including:
- a P-type metal oxide semiconductor (PMOS) field effect transistor (FET) having a source and a drain electrically connected to the voltage input terminal and the voltage output terminal, respectively, and having a gate controlled by the error amplified signal;
- and
- an electrostatic discharge protection device electrically connected to the voltage input terminal and the voltage output terminal, for providing an electrostatic discharge path such that the electrostatic voltage of the voltage output terminal discharges through the electrostatic discharge path, to protect the PMOSFET, wherein the voltage output terminal includes a contact pad for providing an electrical connection to a load circuit.
Dependencies are inferred from the claim text.