Power-insulated-gate field-effect transistor
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorYasuhiko Takemura
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Abstract
To provide a power MISFET using oxide semiconductor. A gate electrode, a source electrode, and a drain electrode are formed so as to interpose a semiconductor layer therebetween, and a region of the semiconductor layer where the gate electrode and the drain electrode do not overlap with each other is provided between the gate electrode and the drain electrode. The length of the region is from 0.5 μm to 5 μm. In such a power MISFET, a power source of 100 V or higher and a load are connected in series between the drain electrode and the source electrode, and a control signal is input to the gate electrode.
Claims40
A power insulated gate field effect transistor comprising:
- a gate electrode;
- an oxide semiconductor layer over the gate electrode, the oxide semiconductor layer comprises a first portion and a second portion;
- one of a source and a drain electrode on the second portion;
- and
- the other of the source and the drain electrode on the first portion,
- wherein:
- a thickness of the first portion is larger than a thickness of the second portion;
- and
- the thickness of the first portion is from 0.5 μm to 5 μm.
A power insulated gate field effect transistor comprising:
- a gate electrode;
- an oxide semiconductor layer over the gate electrode;
- one of a source and a drain electrode on the oxide semiconductor layer;
- and
- the other of the source and the drain electrode on the oxide semiconductor layer,
- wherein:
- the one of the source and the drain electrode overlaps with a part of the gate electrode;
- the other of the source and the drain electrode does note overlap with the gate electrode;
- the oxide semiconductor layer includes a region between the gate electrode and the other of the source and the drain electrode, the region does not overlap with the gate electrode and the other of the source and the drain electrode;
- and
- a length of the region is from 0.5 μm to 5 μm.
A power insulated gate field effect transistor comprising:
- a gate electrode;
- an oxide semiconductor layer over the gate electrode, the oxide semiconductor layer comprises a first portion and a second portion;
- and
- one of a source and a drain electrode on the first portion,
- wherein:
- the second portion includes a channel region;
- a thickness of the first portion is larger than a thickness of the second portion;
- and
- the thickness of the first portion is from 0.5 μm to 5 μm.
Dependencies are inferred from the claim text.