Nand flash memory array having pillar structure and fabricating method of the same

A method of fabricating a NAND flash memory array having a pillar structure, including:

• injecting initial ions into a prepared semiconductor substrate;
• forming silicon fins on the ion-injected substrate in the direction of bit line;
• depositing an oxide layer on the substrate in order to isolate between the fins;
• removing the oxide layer on the silicon fin through a planarization process;
• coating a photoresist on the substrate, where the upper side of the silicon fins is exposed;
• patterning the photoresist in the direction of word line;
• forming trenches with a specific depth and isolated silicon pillars by etching the silicon and the oxide layer along the patterned photoresist and removing the photoresist;
• forming two or more dielectric layers including a charge trap layer through a continuous deposition process on the whole surface of the substrate where the trenches are formed;
• forming sidewall gates which are spaced each other on both sides of the trench by depositing conductive materials onto the dielectric layers and etching the conductive materials;
• and
• forming source/drains by injecting ions into the whole surface of the substrate where the sidewall gates are formed.