3d integrated circuit structure and method for detecting chip mis-alignement

A method for detecting whether chip structures are aligned, comprising:

• forming a first chip structure, which comprises providing a first semiconductor substrate, forming a first insulating layer on the first semiconductor substrate, and forming a first detection structure embedded into the first insulating layer;
• wherein the first detection structure comprises detection bodies positioned on two sides of the first insulating layer, the detection body comprises a first conductor, at least two second conductors, and at least one third conductors;
• wherein the first conductor is located on a side of the first insulating layer and connected with ends of the second conductors;
• the third conductors are formed between the second conductors and insulated from the second conductors, and the ends of the third conductors away from the first conductor are step-wise;
• wherein the vertical distances between the third conductors and the second conductors are equal, and in the direction of the length of the third conductors, the distances between the projections of the ends of the third conductors away from the first conductor which are corresponding to each other and located on the detection bodies on the two sides are substantially the same;
• forming a second chip structure, which comprises providing a second semiconductor substrate, forming a second insulating layer on the second semiconductor substrate, and forming a second detection structure embedded into the second insulating layer;
• wherein the second detection structure comprises a fourth conductor which is located in the middle of the second insulating layer;
• bonding the first detection structures with the second detection structures which are facing to each other, wherein the fourth conductor can be electrically connected with at least one of the third conductors and therefore form a capacitor with the second conductors;
• making a judgement as follows:
• if the capacitances formed respectively between the fourth conductor and the second conductors on the two sides are equal, it is determined that there is not misalignment between the first and the second chip structures;
• if the capacitances formed respectively between the fourth conductor and the second conductors on the two sides are unequal, it is determined that there is misalignment between the first and the second chip structures.