Non-volatile semiconductor memory device and depletion-type mos transistor

A method of manufacturing a non-volatile semiconductor memory device, the non-volatile semiconductor memory device comprising:

• a memory cell array including memory cell transistors arranged therein, the memory cell transistors being provided with a charge accumulation layer formed on a semiconductor substrate via a gate insulating film;
• and
• a peripheral circuit configured to drive the memory cell transistors, the peripheral circuit including a first transistor,
• the method comprising:
• forming a first element isolation insulating film on the semiconductor substrate to form a first active area of the first transistor;
• implanting a first conductivity type impurity into a first region of the semiconductor substrate to form a first channel region of the first transistor in a part of the first active area;
• stacking a first gate insulating layer of the first transistor and a first gate electrode of the first transistor on a part of the first channel region;
• and
• implanting the first conductivity type impurity into a second region of the semiconductor substrate by using the first gate electrode as a mask to form overlapping regions where the second region overlaps the first channel region and to form first source-drain regions of the first transistor where the second region excluding the overlapping regions in the first active area.