Early Read After Write Operation Memory Device, System And Method

A memory controller to be coupled to first and second memory banks via a signal path, the memory controller comprising:

• an interface;
• a first storage circuit to store a plurality of write commands;
• and
• logic to output a write command, at the interface, during a first interval of time to the first memory bank via the signal path, the write command obtained from the plurality of write commands, the logic to output a read command, at the interface, during a second interval of time to the second memory bank via the signal path,
• wherein the write command initiates storing write data in the first memory bank and the read command initiates accessing read data from the second memory bank,
• wherein the second interval of time occurs immediately after the first interval of time.

A method of operation in a memory controller having an interface, the memory controller to be coupled to a first memory bank and a second memory bank via common signal path, the method comprising:

• outputting, at the interface, a write address and write data to the first memory bank via the common signal path;
• and
• outputting, at the interface, a read address to the second memory bank via the common signal path,
• wherein the write address is output during a first interval of time and the read address is output during a second interval of time,
• wherein the second interval of time is immediately after the first interval of time.