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US 2011/0299344 A1Published application
A new low voltage and low power memory cell based on nano current voltage divider controlled low voltage sense mosfet
AssigneeSichuan Kiloway Electronics Inc.
InventorsJack Z. Peng, David Fong
Life of this patent
Estimating the term…
Abstract
A memory cell has at least two word lines and at least two bit lines. The cell also has a first select device being connected to at least one word line and one bit line and a gate capacitor element connected to at least one word line and the first select device. The cell also has a sense device being connected in series to the gate capacitor element and the first select device. The sense device is connected to at least two bit lines.
Claims27
A memory circuit comprising:
- at least two word lines;
- at least two bit lines;
- a first select device being connected to at least one word line and one bit line;
- a gate capacitor element connected to at least one word line and the first select device;
- and
- a sense device being connected in series to the gate capacitor element and the first select device, the sense device being connected to at least two bit lines.
3 more elements
A memory circuit comprising:
- at least two word lines;
- at least two bit lines;
- a first select device being connected to at least one word line and one bit line;
- a gate capacitor element connected to at least one word line and the first select device;
- and
- a second sense device being connected in series to the gate capacitor element and the first select device, the second sense device is connected to at least two bit lines, wherein the gate capacitor element is a memory cell being selected from the group consisting of a ROM, an EPROM, an EEPROM, a Flash memory cell, a PCRAM, a FCRAM, an MRAM, and an anti-fuse element.
3 more elements
A circuit comprising:
- at least two word lines;
- at least two bit lines;
- a first select device being connected to at least one word line and one bit line;
- a gate capacitor element connected to at least one word line and the first select device;
- and
- a second sense device being connected in series to the gate capacitor element and the first select device, the second sense device being connected to at least two bit lines, wherein the gate capacitor element is a P type field effect transistor, wherein the first select device is a P type field effect transistor and wherein the sense device is P type field effect transistor.
3 more elements
A memory circuit comprising:
- at least two word lines;
- at least two bit lines;
- a first select device being connected to at least one word line and one bit line;
- a gate capacitor element connected to at least one word line and the first select device;
- a sense device being connected in series to the gate capacitor element and the first select device, the sense device being connected to at least two bit lines;
- a decoder circuit being connected to the sense device;
- and
- an amplifier being connected to the decoder circuit.
5 more elements
A memory circuit comprising:
- a first word line;
- a second word line;
- a first bit line;
- a second bit line;
- a first select device being connected to the second word line and the first bit line;
- a gate capacitor element connected to the first word line and the first select device;
- a sense device being connected in series to the gate capacitor element and the select device, the sense device being connected to the first bit line and the second bit line;
- a decoder circuit being connected to the sense device and the first select device;
- a current limiting circuit being connected to the decoder circuit;
- and
- wherein the gate capacitor element is a field effect transistor, the first select device is a field effect transistor, and the sense device is a field effect transistor.
8 more elements
A method comprising:
- providing a first transistor connected to a first word line;
- providing a second transistor connected to a second word line;
- providing a third transistor connected to the first and the second transistor and connected to a first and a second bit line;
- programming by elevating the first word line to a predetermined voltage;
- switching on the second word line;
- and
- grounding the first bit line for a predetermined time period.
4 more elements
Dependencies are inferred from the claim text.