Carrier-free semiconductor package and fabrication method

A method for fabricating a carrier-free semiconductor package, comprising the steps of:

• preparing a metal carrier having a first surface with a plurality of recess grooves and a plurality of metal studs complementary to the recess grooves and a second surface opposite to the first surface;
• filling the recess grooves with a first encapsulant in a manner that upper surfaces of the metal studs are exposed from the first encapsulant, wherein the first encapsulant that a top surface and an opposing bottom surface;
• forming a plurality of conductive traces on the top surface of the first encapsulant and the upper surfaces of the metal studs and electrically connected to the metal studs;
• disposing a semiconductor chip on the first encapsulant and electrically connecting the semiconductor chip to each of the conductive traces;
• forming a second encapsulant on the first surface of the metal carrier to encapsulate the semiconductor chip and each of the conductive traces;
• and
• removing a portion of the metal carrier from the second surface thereof so as to expose lower surfaces of the metal studs and the bottom surface of the first encapsulant.

A method for fabricating a carrier-free semiconductor package, comprising the steps of:

• preparing a metal carrier having a first surface with a plurality of recess grooves and metal studs and a second surface opposite to the first surface;
• filling the recess grooves with a first encapsulant, with upper surfaces of the metal studs being exposed from the first encapsulant, wherein the first encapsulant has a top surface and an opposing bottom surface;
• forming a plurality of conductive traces on the top surface of the first encapsulant and the upper surfaces of the metal studs and electrically connected to the metal studs;
• forming a second encapsulant on the first encapsulant and each of the conductive traces, each of the conductive traces being partially exposed from the second encapsulant;
• forming build-up traces on the second encapsulant and the exposed parts of the conductive traces;
• forming a plating layer on each of terminals of the build-up traces;
• disposing a semiconductor chip on the second encapsulant and electrically connecting the semiconductor chip to the build-up traces;
• forming a third encapsulant on the second encapsulant to encapsulate the semiconductor chip and each of the build-up traces;
• and
• removing a part of the metal carrier from the second surface thereof so as to expose lower surfaces of the metal studs and the bottom surface of the first encapsulant.

A carrier-free semiconductor package, comprising:

• a plurality of metal studs spaced from each other;
• a first encapsulant having a top surface and an opposite bottom surface, wherein sides of the metal studs are encapsulated by the first encapsulant, and upper and lower surfaces of the metal studs are exposed from the top and bottom surfaces of the first encapsulant, respectively;
• a semiconductor chip disposed on the top surface of the first encapsulant and electrically connected to each of the metal studs;
• and
• a second encapsulant formed on the top surface of the first encapsulant and encapsulating the semiconductor chip.

A carrier-free semiconductor package, comprising:

• a plurality of metal studs spaced from each other;
• a first encapsulant having a top surface and an opposite bottom surface, wherein sides of the metal studs are encapsulated by the first encapsulant, and upper and lower surfaces of the metal studs are exposed from the top and bottom surfaces of the first encapsulant, respectively;
• a plurality of conductive traces disposed on the top surface of the first encapsulant and electrically connected to each of the metal studs;
• a semiconductor chip disposed on the top surface of the first encapsulant and electrically connected to each of the conductive traces;
• and
• a second encapsulant formed on the top surface of the first encapsulant and encapsulating the semiconductor chip and each of the conductive traces.

A carrier-free semiconductor package, comprising:

• a plurality of metal studs spaced from each other;
• a first encapsulant having an top surface and an opposite bottom surface, wherein sides of the metal studs are encapsulated by the first encapsulant, and upper and lower surfaces of the metal studs are exposed from the top and bottom surfaces of the first encapsulant, respectively;
• a plurality of conductive traces disposed on the top surface of the first encapsulant and electrically connected to the metal studs;
• a second encapsulant formed on the first encapsulant and the plurality of conductive traces, each of the conductive traces being at least partially exposed from the second encapsulant;
• a plurality of build-up traces disposed on the second encapsulant and the exposed conductive traces;
• a semiconductor chip disposed on a top surface of the second encapsulant and electrically connected to the build-up traces;
• and
• a third encapsulant formed on the top surface of the second encapsulant and encapsulating the semiconductor chip and each of the build-up traces.