Contact resistivity reduction in transistor devices by deep level impurity formation
AssigneeInternational Business Machines Corporation
InventorsTak Hung Ning, Zhen Zhang
Life of this patent
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Abstract
A method of forming a low resistance contact structure in a semiconductor device includes forming a doped semiconductor region in a semiconductor substrate; forming a deep level impurity region at an upper portion of the doped semiconductor region; activating dopants in both the doped semiconductor region and the deep level impurity region by annealing; and forming a metal contact over the deep level impurity region so as to create a metal-semiconductor interface therebetween.
Claims30
A method of forming a low resistance contact structure in a semiconductor device, the method comprising:
- forming a doped semiconductor region in a semiconductor substrate;
- forming a deep level impurity region at an upper portion of the doped semiconductor region;
- activating dopants in both the doped semiconductor region and the deep level impurity region by annealing;
- and
- forming a metal contact over the deep level impurity region so as to create a metal-semiconductor interface therebetween.
A low resistance contact structure in a semiconductor device comprising:
- a doped semiconductor region formed in a semiconductor substrate;
- a deep level impurity region formed at an upper portion of the doped semiconductor region;
- and
- a metal contact formed over the deep level impurity region so as to create a metal-semiconductor interface therebetween.
A method of forming a low resistance contact structure in a field effect transistor (FET) device, the method comprising:
- forming a doped source/drain region in a silicon substrate;
- forming a deep level impurity region at an upper portion of the doped source/drain region;
- and
- forming a silicide metal contact over the deep level impurity region to create a metal-silicon interface;
- wherein the deep level impurity region has a depth greater than or equal to a depletion width of the doped source/drain region, which corresponds to a band-bending region of the metal-silicon interface.
A low resistance contact structure in a field effect transistor (FET) device, comprising:
- a doped source/drain region formed in a silicon substrate;
- a deep level impurity region formed at an upper portion of the doped source/drain region;
- and
- a silicide metal contact formed over the deep level impurity region so as to create a metal-silicon interface therebetween;
- wherein the deep level impurity region has a depth greater than or equal to a depletion width of the doped source/drain region, which corresponds to a band-bending region of the metal-silicon interface.
Dependencies are inferred from the claim text.