Cell Library, Integrated Circuit, and Methods of Making Same
AssigneesSTMicroelectronics S.r.l., Commissariat A L'energie Atomique Et Aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
InventorsOlivier Menut, Laurent Bergher, Emek Yesilada, Yorick Trouiller, Franck Foussadier, Raphaël Bingert
Life of this patent
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Abstract
A cell library intended to be used to form an integrated circuit, this library defining a first cell including a first MOS transistor of minimum dimensions, and a second cell including a second MOS transistor of lower leakage current, wherein the second cell takes up the same surface area as the first cell, and the second MOS transistor has a gate of same length as the gate of the first MOS transistor across at least a first width in its central portion, and of greater length across at least a second width on either side of the central portion.
Claims20
A cell library intended to be used to form an integrated circuit, said library defining a first cell including a first MOS transistor of a minimum dimension, and a second cell including a second MOS transistor of lower leakage current, wherein the second cell takes up the same surface area as the first cell, and the second MOS transistor has a gate of same length as the gate of the first MOS transistor across at least a first width in its central portion, and of greater length across at least a second width on either side of the central portion.
A method for synthesizing at least a portion of an integrated circuit based on a cell library, comprising, for each MOS transistor of the integrated circuit, the steps of:
- selecting a first cell if a first MOS transistor is intended to operate at maximum speed;
- and
- selecting a second cell if a second MOS transistor is not intended to operate at maximum speed;
- wherein the second cell takes up the same surface area as the first cell, and the second MOS transistor has a gate of same length as the gate of the first MOS transistor across at least a first width in its central portion, and of greater length across at least a second width on either side of the central portion.
An integrated circuit comprising:
- a plurality of cells;
- wherein a first one of said plurality of cells includes a first MOS transistor having a feature of a minimum dimension, and a second one of said plurality of cells includes a second MOS transistor having lower leakage current than said first MOS transistor, and
- wherein the second cell takes up the same surface area as the first cell, and the second MOS transistor has a gate of same length as the gate of the first MOS transistor across at least a first width in its central portion, and of greater length across at least a second width on at least one side of the central portion.
A method of manufacturing an integrated circuit comprising:
- identifying a first circuit portion having a first design requirement of a first function and wherein operating speed is a more important parameter than leakage current;
- identifying a second circuit portion having a second design requirement of the first function and wherein operating speed is not a more important parameter than leakage current;
- manufacturing a first cell meeting the first design requirement, the first cell occupying a first amount of surface area and comprising a first transistor having a first gate length;
- and
- manufacturing a second cell meeting the second design requirement, the second cell occupying the same amount of surface area as the first cell and comprising a second transistor having a gate of same length as the gate of the first transistor across at least a first portion of the gate of the second transistor, and of greater length across at least a second portion the second gate.
Dependencies are inferred from the claim text.