Memory Having an ECC System
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsAdrian Earle, Raviprakrash S. Rao, Vineet Joshi
Life of this patent
Estimating the term…
Abstract
An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.
Claims21
1-20. (canceled)
A method of testing error correction code (ECC) logic circuitry of a memory device having a parity array, the method comprising:
- writing test data directly to the memory device;
- and
- correcting the test data with the ECC logic circuitry.
A method of testing error correction code (ECC) logic circuitry of a memory device having a parity array, the method comprising:
- writing test data directly to the memory device;
- and
- correcting the test data with the ECC logic circuitry;
- wherein the step of writing test data comprises:
- disabling said ECC logic circuitry;
- coupling the parity array to input/output circuitry thereby bypassing the ECC logic circuitry;
- and
- providing the test data from the input/output circuitry.
A method of testing error correction code (ECC) logic circuitry of a memory device having a parity array, the method comprising:
- writing test data directly to the memory device;
- and
- correcting the test data with the ECC logic circuitry;
- wherein the step of correcting the test data comprises:
- enabling the ECC logic circuitry;
- coupling the parity array to the ECC logic circuitry;
- providing the test data to the ECC logic circuitry;
- and
- correcting the test data to provide corrected test data to input/output circuitry.
Dependencies are inferred from the claim text.