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US 2011/0258420 A1Published application
Execution migration
AssigneeMassachusetts Institute of Technology
InventorsSrinivas Devadas, Omer Khan, Mieszko Lis, Keun Sup Shim, Myong Hyon Cho
Life of this patent
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Abstract
An execution migration approach includes bringing the computation to the locus of the data: when a memory instruction requests an address not cached by the current core, the execution context (current program counter, register values, etc.) moves to the core where the data is cached.
Claims42
A processing method comprising:
- processing instructions for tasks at each of a plurality of processing elements of a multiple processor system, the instructions including memory access instructions for accessing a memory having a plurality of disjoint regions, each region corresponding to a different processing element of the plurality of processing elements, wherein the processing includes,
- processing instructions for a first task at a first processing element of the plurality of processing elements, including processing memory access instructions for accessing data in the memory, wherein at least some of the memory access instructions reference memory regions not corresponding to the first processing element and at least some of the memory access instructions reference a memory region corresponding to the first processing element, and
- for at least some of the memory access instructions referencing the memory region not corresponding to the first processing element, transferring a locus of execution of the first task from the first processing element to a different processing element.
An multiple processor computing system comprising:
- an interface to a first memory;
- and
- a plurality of processing elements, each processing element being associated with a corresponding second memory of a plurality of second memories, the processing elements together being configured to concurrently execute multiple tasks;
- wherein each second memory is associated with a corresponding set of memory locations of the first memory such that in operation each memory location in the sets of memory locations that is accessible from the processing elements is associated with at most one of the second memories.
1 more element
Dependencies are inferred from the claim text.