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US 2011/0258419 A1Published application
Attaching And Virtualizing Reconfigurable Logic Units To A Processor
OwnerAndrew F. Glewinventor
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Abstract
In one embodiment, the present invention includes a pipeline to execute instructions out-of-order, where the pipeline has front-end stages, execution units, and back-end stages, and the execution units are coupled between dispatch ports of the front-end stages and writeback ports of the back-end stages. Further, a reconfigurable logic is coupled between one of the dispatch ports and one of the writeback ports. Other embodiments are described and claimed.
Claims20
An apparatus comprising:
- a processor including a register to store a thread identifier and a pipeline having a plurality of stages to execute instructions out of order, the stages including a plurality of front-end stages, a plurality of execution units, and a plurality of back-end stages;
- and
- a first reconfigurable logic unit including configurable logic elements coupled between a dispatch port and a writeback port of the pipeline, wherein the first reconfigurable logic unit is to perform a reconfigurable logic function indicated by a first instruction including a reconfigurable logic opcode, wherein first logic of the first reconfigurable logic unit is to determine whether the reconfigurable logic function is loaded based on the reconfigurable logic opcode and the thread identifier, and if so to provide a physical reconfigurable logic opcode and a configuration number associated with a configuration of the configurable logic elements, and otherwise to cause an exception.
An apparatus comprising:
- a general-purpose processor including a pipeline having a plurality of stages to execute instructions out-of-order, the stages including a plurality of front-end stages, a plurality of execution units, and a plurality of back-end stages;
- and
- a reconfigurable logic unit coupled within a pipeline of the general-purpose processor unit including configurable logic elements, wherein the reconfigurable logic unit is to perform a reconfigurable logic function indicated by an instruction, the instruction including a reconfigurable logic control block virtual address and a reconfigurable logic opcode, and the reconfigurable logic unit including a mapping table to map a tuple of the instruction to a physical reconfigurable logic opcode and configuration number associated with a configuration of the configurable logic elements.
A method comprising:
- receiving a first instruction and a thread identifier in a reconfigurable logic unit from a processor coupled to the reconfigurable logic unit;
- determining whether a reconfigurable logic function is loaded in the reconfigurable logic unit based on the reconfigurable logic opcode and the thread identifier;
- and
- if so, providing a physical reconfigurable logic opcode and a configuration number associated with a configuration of configurable logic elements of the reconfigurable logic unit.
1 more element
Dependencies are inferred from the claim text.