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US 2011/0255335 A1Published application
Charge trap memory having limited charge diffusion
OwnerAlessandro Grossiinventor
Life of this patent
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Abstract
Subject matter disclosed herein relates to flash memory, and more particularly to a charge trap memory and a process flow to form same.
Claims24
A method of fabricating a memory device, the method comprising:
- etching a first semiconductor layer that is at least partially covering peripheral circuitry and an isolated region on a substrate to form trenches to expose said isolated region;
- and
- etching said isolated region at the bottom of said trenches to deepen said trenches to substantially below said first semiconductor layer.
A memory device comprising:
- an array of charge trap memory cells comprising:
- an active dielectric stack conformally covering semiconductor lines formed on an isolated region on a substrate;
- and
- a conductive layer at least partially covering said active dielectric stack, wherein at least portions of said conductive layer extend to substantially below said semiconductor lines.
1 more element
A system comprising:
- a memory device comprising:
- an array of charge trap memory cells comprising
- an active dielectric stack conformally covering semiconductor lines formed on an isolated region on a substrate, and
- a conductive layer at least partially covering said active dielectric stack, wherein at least portions of said conductive layer extend to substantially below said semiconductor lines;
- and
- a memory controller to operate said memory device, said
- a processor to host one or more applications and to initiate write commands to said memory controller to provide access to memory cells in said memory arrays.
4 more elements
Dependencies are inferred from the claim text.