Nonvolatile semiconductor memory device

Abstract

A nonvolatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array configured by memory cells each provided between a first line and a second line and each including a variable resistor. A control circuit applies to any one of the memory cells through the first and second lines a voltage necessary for an operation of any one of the memory cells. A current limiting circuit is connected to the first line and limits a current flowing across the memory cell during an operation to a certain limit value. During an operation, the control circuit supplies a first voltage to the first line while supplying to the second line a second voltage. The second voltage lowers over time.

Dependencies are inferred from the claim text.