Semiconductor memory device
AssigneePanasonic Corporation
InventorsYasuo MURAKUKI, Shunichi IWANARI, Yoshiaki NAKAO
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Abstract
The demand for reducing the size and increasing the degree of integration of semiconductor memory devices has increased. In a semiconductor memory device, a smoothing capacitor which has to be provided therein for stabilizing a power supply voltage etc. is formed in an underlying layer of memory cells A and B to overlap the two memory cells A and B which are adjacent each other. Thus, an area occupied by the smoothing capacitor having a large capacity can be reduced to increase the degree of integration, and the smoothing capacitor having a large capacity can be provided in the semiconductor memory device.
Claims15
A semiconductor memory device, comprising:
- a plurality of bit lines arranged in a column direction;
- a plurality of word lines arranged in a row direction;
- and
- a memory cell array including a plurality of memory cells which are arranged at intersections of the bit lines and the word lines, each memory cell including a selective element and a first capacitive element connected in series between an associated one of the bit lines and a plate interconnect, the selective element having a control terminal connected to an associated one of the word lines,
- wherein in an underlying layer of the first capacitive element, a second capacitive element is provided to overlap two or more of the memory cells.
Dependencies are inferred from the claim text.