Encoding Data for Storage in a Content Addressable Memory
AssigneeNetLogic Microsystems, Inc.
InventorKee Park
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Abstract
An encoding scheme is disclosed that allows a CAM device to selectively store, within each cell of a row of the CAM device, either a single bit of a binary value or two bits of an encoded data word encoded from the binary value. By storing two bits of the encoded data word in each CAM cell, data may be stored more efficiently and CAM systems may consume less power. The encoded data words can be balanced data words that have equal number of logic high and logic low values.
Claims31
A content addressable memory (CAM) device, comprising:
- a CAM array including a plurality of rows, each row including a number T of quaternary CAM cells coupled to a match line;
- and
- a programmable write circuit coupled to the CAM array and configured to selectively store, within each CAM cell of a selected CAM row, either a single data bit of a first data word or two data bits of an encoded data word, wherein none of the data bits are mask bits.
A content addressable memory (CAM) device, comprising:
- a CAM array including a plurality of rows, each row including a number T of quaternary CAM cells;
- and
- a programmable write circuit coupled to the CAM array and configured to store, within a selected row, a single data bit of a first data word in each of a first set of CAM cells in the selected row, and two data bits of an encoded data word in each of a second set of CAM cells in the selected row, wherein none of the data bits are mask bits.
A content addressable memory (CAM) device including a plurality of CAM blocks, each CAM block comprising:
- a CAM array including a plurality of rows, each row including a number T of quaternary CAM cells;
- and
- a programmable write circuit coupled to the CAM array in the corresponding block and configured to store, in each CAM cell within a selected row of the CAM array, either a single data bit of a first data word or two data bits of an encoded data word, wherein the programmable write circuit comprises:
- a data encoder circuit having an input to receive the first data word and configured to generate the encoded data word;
- and
- a multiplexer having a first input to receive the first data word, having a second input to receive the encoded data word, having a control input to receive a mode select signal, and having an output coupled to the CAM array.
Dependencies are inferred from the claim text.