Display device and electronic appliance

A display device comprising:

• a display area in which a plurality of pixels, a plurality of gate signal lines, and a plurality of source signal lines divided into N groups are arranged in a matrix, N being a natural number;
• a scan line driver circuit configured to control a timing of selecting any one of the plurality of gate signal lines;
• and
• a signal line driver circuit configured to control, in a period during which the scan line driver circuit selects any one of the plurality of gate signal lines, a timing of outputting a first signal to all the plurality of source signal lines divided into N groups and then outputting a second signal sequentially to the plurality of source signal lines divided into N groups, group by group,
• wherein each of the plurality of pixels includes a transistor and a display element being sandwiched between a pixel electrode and a common electrode and having memory properties,
• wherein a first terminal of the transistor is electrically connected to any one of the plurality of source signal lines,
• wherein a second terminal of the transistor is electrically connected to the pixel electrode, and
• wherein a gate of the transistor is electrically connected to any one of the plurality of gate signal lines.

A display device comprising:

• a display area in which a plurality of pixels, a plurality of gate signal lines, and a plurality of source signal lines divided into N groups are arranged in a matrix, N being a natural number;
• a scan line driver circuit configured to control a timing of selecting any one of the plurality of gate signal lines;
• and
• a signal line driver circuit configured to control, in a period during which the scan line driver circuit selects any one of the plurality of gate signal lines, a timing of outputting a first signal to the source signal lines in the second to N-th groups, and then outputting a second signal to the source signal lines in the first group, and then outputting a second signal sequentially to the source signal lines in the second to N-th groups, group by group,
• wherein each of the plurality of pixels includes a transistor and a display element being sandwiched between a pixel electrode and a common electrode and having memory properties,
• wherein a first terminal of the transistor is electrically connected to any one of the plurality of source signal lines,
• wherein a second terminal of the transistor is electrically connected to the pixel electrode, and
• wherein a gate of the transistor is electrically connected to any one of the plurality of gate signal lines.