Thin film transistor array panel and method for manufacturing the same

A method for manufacturing a thin film transistor array panel, the method comprising:

• forming a gate electrode, a gate pad, and a gate line on a substrate;
• forming a gate insulating layer on the gate line;
• forming a data line, including a source electrode, a data pad, and a drain electrode facing the source electrode, on the gate insulating layer;
• forming a passivation layer on the gate insulating layer, the data line, and the drain electrode;
• forming a negative photosensitive organic layer on the passivation layer;
• forming a protrusion and depression pattern, and a plurality of openings in the negative photosensitive organic layer, by using a photomask exposed to a light, the protrusion and depression pattern overlapping the gate pad and the data pad;
• heat treating the negative photosensitive organic layer to form an insulating layer including a first portion of a first thickness, and a second portion of a second thickness which is smaller than the first thickness;
• etching the passivation layer and the gate insulating layer by using the insulating layer as a mask, to form a first contact hole exposing the drain electrode, a second contact hole exposing the gate pad, and a third contact hole exposing the data pad;
• and
• forming a pixel electrode, a first contact assistant, and a second contact assistant on the insulating layer,
• wherein
• the pixel electrode overlaps the first portion of the insulating layer,
• the first and second contact assistants overlap the second portion of the insulating layer, and
• the second thickness of the second portion is less than about 1.5 micrometers.