Phase interpolator and a delay circuit for the phase interpolator

A delay circuit comprising:

• an inverter coupled between an input terminal of the delay circuit and an output terminal of the delay circuit;
• and
• one or more capacitive elements coupled to the output terminal of the delay circuit to enable generation of desired delay, each capacitive element of the one or more capacitive elements comprising
• a positive metal oxide semiconductor (PMOS) transistor having drain and source coupled to the output terminal of the delay circuit and having gate connection that is configurable using a control signal to enable the PMOS transistor to provide capacitance, and
• a negative metal oxide semiconductor (NMOS) transistor with source and drain coupled to the output terminal of the delay circuit and having gate connection that is configurable using the control signal to enable the NMOS transistor to provide capacitance.

A method comprising:

• rotating phase of an input clock to generate a first phase rotated signal in a first time period;
• rotating phase of the input clock to generate a second phase rotated signal in a second time period;
• selectively providing one of the first phase rotated signal and the second phase rotated signal as a phase rotated signal to a delay locked loop;
• and
• generating a plurality of phase shifted outputs by the delay locked loop from the phase rotated signal.