Chip Area Optimized Pads
AssigneeNewport Media, Inc.
InventorNabil Yousef Wasily
Life of this patent
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Abstract
An optimized semiconductor chip pad configuration. The pad includes a pad circuit area Ap, a first dimension x and a second dimension y, in a chip having N number of pins on each side. The pins include a longitudinal axis, and the chip includes a chip core of length Lc. The method includes determining the first dimension x by dividing the length Lc by the N, determining the second dimension y by dividing the pad circuit area Ap by a result of a division of the length Lc by the N, and creating a semiconductor area pad that includes pins with the longitudinal axis positioned parallel to the chip core. A stack of circuits is designed in the chip to fit in the pad based on the first dimension x and the second dimension y.
Claims20
A method of optimizing a semiconductor chip pad configuration, wherein said pad comprises a pad circuit area Ap, a first dimension x, and a second dimension y, in a chip having N number of pins on each side, wherein said pins comprise a longitudinal axis, and wherein said chip comprises a chip core of length Lc, said method comprising:
- determining said first dimension x by dividing said length Lc by said N;
- determining said second dimension y by dividing said pad circuit area Ap by a result of a division of said length Lc by said N;
- and
- creating a semiconductor area pad comprising pins with said longitudinal axis positioned parallel to said chip core.
An integrated circuit comprising:
- a semiconductor core of length Lc;
- a plurality of sides of said core each having N number of pins;
- and
- a plurality of semiconductor area chip pads, wherein each pad comprises:
- a first dimension x that is determined by dividing said length Lc by said N;
- and
- a second dimension y that is determined by dividing an area of said pad Ap by a result of a division of said length Lc by said N,
- a stack of circuits that fit in said pad based on said first dimension x and said second dimension y,
- wherein said pins comprise a longitudinal axis positioned parallel to said semiconductor core.
A semiconductor area optimized integrated circuit chip pad having an area Ap mounted in a chip having N number of pins on each side, wherein said chip comprises a semiconductor core of length Lc, said semiconductor area optimized pad comprising:
- a first dimension x that is determined by dividing said length Lc by said N;
- and
- a second dimension y that is determined by dividing said area of said semiconductor area optimized pad Ap by a result of a division of said length Lc by said N,
- wherein said pins comprise a longitudinal axis positioned parallel to said semiconductor core.
Dependencies are inferred from the claim text.