Cmp-first damascene process scheme
AssigneeGlobalfoundries Inc.
InventorsJihong Choi, Tibor Bolom
Life of this patent
Estimating the term…
Abstract
An improved metal interconnect is formed with reduced metal voids and dendrites. An embodiment includes forming a mask layer on a dielectric layer, forming openings in the mask and dielectric layers, depositing a planarization layer over the mask layer and filling the openings, planarizing to remove the mask layer, removing the planarization layer from the openings, and filling the openings with metal. The planarization step prior to depositing the metal removes the etch undercut that occurs during formation of the openings and reduces the aspect ratio in the openings, thereby improving metal fill uniformity.
Claims20
A method of fabricating a metal interconnect, the method comprising:
- forming a mask layer on a dielectric layer;
- forming openings in the mask and dielectric layers;
- depositing a planarization layer over the mask layer and filling the openings;
- planarizing to remove the mask layer;
- removing the planarization layer from the openings;
- and
- filling the openings with metal.
A semiconductor device comprising:
- a dielectric layer;
- and
- metal interconnects in the dielectric layer, the metal interconnects being formed by:
- forming a hard mask layer on the dielectric layer;
- forming trenches in the hard mask and dielectric layers, whereby an undercut portion is formed at an interface between the mask layer and dielectric layer;
- planarizing by conducting chemical mechanical polishing (CMP) to remove the mask layer and undercut portion;
- and
- filling the trenches with metal.
A method of fabricating a semiconductor device, the method comprising:
- depositing a dielectric layer over a substrate;
- forming a hard mask layer on the dielectric layer;
- lithographically patterning the hard mask layer;
- etching the dielectric layer through the patterned hard mask to form trenches and via/contact openings, whereby an undercut portion is formed at an interface between the mask layer and dielectric layer;
- depositing an optical planarization layer over the hard mask layer filling the trenches and via/contact openings;
- planarizing by conducting chemical mechanical polishing (CMP) to remove the mask layer and undercut portion;
- wet etching to remove the optical planarization layer;
- depositing barrier and seed metal in the trenches and via/contact openings;
- copper (Cu) plating to fill the trenches and via/contact openings and forming an overburden on the dielectric layer;
- and
- conducting CMP to remove the overburden.
Dependencies are inferred from the claim text.