Semiconductor Memory Devices Having Strain Layers Therein That Increase Device Performance And Methods of Forming Same

Abstract

Integrated circuit memory devices include a semiconductor word line having an electrically insulating strain layer directly contacting an upper surface thereof. The strain layer, which has a contact opening therein, has a sufficiently high degree of internal compressive strain therein to thereby impart a net tensile stress within at least a first portion of the semiconductor word line. A P-N junction diode is also provided on the semiconductor word line. The diode includes a first terminal (e.g., cathode, anode) electrically coupled through the opening in the strain layer to the surface of the semiconductor word line. A data storage element (e.g., MRAM, FRAM, PRAM, RRAM, etc.) may also be provided, which has a current carrying terminal electrically coupled to a second terminal of the p-n junction diode.

Dependencies are inferred from the claim text.