ESD Protection Structures on SOI Substrates

An electrostatic discharge (ESD) protection circuit comprising:

• a buried oxide layer;
• a semiconductor layer over the buried oxide layer;
• a first MOS device comprising:
• a first gate over the semiconductor layer;
• a first well region in the semiconductor layer and having a portion underlying the first gate, wherein the first well region comprises a first end portion adjacent a first end of the first gate, and a second end portion adjacent a second end of the first gate, and wherein the first well region is not directly connected to any ground;
• and
• a first source region and a first drain region in the semiconductor layer;
• a metal line interconnecting the first and the second end portions of the first well region;
• and
• a second MOS device comprising:
• a second gate over the semiconductor layer;
• and
• a second well region in the semiconductor layer and having a portion underlying the second gate, wherein the second well region comprises a third end portion connected to the second end portion of the first gate, and a fourth end portion directly connected to a ground.