Semiconductor device and method of fabricating the same
OwnerChang-Sup Lee, Jongho Park +2inventors
InventorsChang-Sup Lee, Jongho Park, Sung-Hun Lee, Ki-Yong Kim
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Abstract
A semiconductor device includes a plurality of gate structures disposed on a substrate. Respective gate structures may include a lower control gate layer and an upper control gate layer. The upper control gate layer may be disposed on the lower control gate layer and may include a different material from the lower control gate layer. The semiconductor device may further include insulation patterned layers disposed in gap regions defined between the gate structures adjacent to each other. Upper surfaces of the insulation patterned layers may be lower than an upper surface of the lower control gate layer.
Claims15
A semiconductor device comprising:
- a plurality of gate structures disposed on a substrate, respective gate structures including a lower control gate layer and an upper control gate layer, the upper control gate layer being disposed on the lower control gate layer and including a different material from the lower control gate layer;
- and
- insulation patterned layers disposed in gap regions defined between the respective gate structures adjacent to each other, upper surfaces of the insulation patterned layers being lower than an upper surface of the lower control gate layer.
The semiconductor device of claim 5, wherein the lower control gate layer includes a first upper surface and second upper surfaces disposed on both sides of the first upper surface, the second upper surfaces being lower than the first upper surface and higher than the upper surfaces of the insulation patterned layers.
12-17. (canceled)
A semiconductor device comprising:
- a first gate structure including a lower control gate layer and an upper control gate layer, the upper control gate layer including a metal silicide;
- a second gate structure including a lower control gate and an upper control gate layer and being distant from the first gate structure at a first space width;
- and
- a first isolation patterned layer filling a gap between the first and the second gate structure and having an upper surface lower than an upper surface of the lower control gate layer of the first gate structure.
Dependencies are inferred from the claim text.