Gate-All-Around CMOSFET devices
AssigneeShanghai Institute of Microsystem and Information Technology, Chinese Academy
InventorsDeyuan Xiao, Xi Wang
Life of this patent
Estimating the term…
Abstract
A GAA (Gate-All-Around) CMOSFET device includes a semiconductor substrate, a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The surfaces of the first channel and the second channel are substantially surrounded by the gate region. A buried insulation layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the semiconductor substrate to isolate them from one another. The structure is simple, compact and highly integrated, has high carrier mobility, and avoids polysilicon gate depletion and short channel effect.
Claims20
A Gate-All-Around CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) device comprising a semiconductor substrate, a PMOS region having a first channel, an NMOS region having a second channel, and a gate region, wherein the NMOS region is disposed above the semiconductor substrate, and the PMOS region is disposed above the NMOS region, wherein
- the NMOS region and the PMOS region each comprises a source region and a drain region located at the two opposite ends of the channel thereof;
- the surfaces of the first channel and the second channel are substantially surrounded by the gate region;
- a first buried insulation layer is disposed between the PMOS region and the NMOS region;
- and
- a second buried insulation layer is disposed between the NMOS region and the semiconductor substrate.
A Gate-All-Around CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) device comprising a semiconductor substrate, a PMOS region having a first channel and disposed above the semiconductor substrate, an NMOS region having a second channel and disposed above the PMOS region, and a gate region, wherein
- the PMOS region and the NMOS region each comprises a source region and a drain region located at the two opposite ends of the channel thereof;
- the surfaces of the first channel and the second channel are substantially surrounded by the gate region;
- a first buried insulation layer is disposed between the PMOS region and the NMOS region;
- and
- a second buried insulation layer is disposed between the PMOS region and the semiconductor substrate.
Dependencies are inferred from the claim text.