Vertical jfet limited silicon carbide metal-oxide semiconductor field effect transistors

A silicon carbide metal-oxide semiconductor field effect transistor comprising:

• a silicon carbide drift layer of a first conductivity type;
• spaced apart silicon carbide well regions of a second conductivity type adjacent the drift layer;
• and
• a silicon carbide limiting region of the first conductivity type disposed between the well regions and the drift layer, the limiting region comprising first portions laterally extending along respective floors of the well regions and second portions extending along respective sidewalls of the well regions, wherein the first and second portions of the limiting region have higher carrier concentrations than the drift layer.

A silicon carbide metal-oxide semiconductor field effect transistor unit cell, comprising:

• an n-type silicon carbide drift layer;
• a first p-type silicon carbide region on the drift layer;
• a first n-type silicon carbide region within the first p-type silicon carbide region;
• and
• an n-type silicon carbide limiting region disposed between the first p-type silicon carbide region and the drift layer, the limiting region comprising a lateral portion extending beneath the first p-type silicon carbide region and a vertical portion extending along a sidewall of the first p-type silicon carbide region, wherein the lateral and vertical portions of the limiting region have respective carrier concentrations that are greater than a carrier concentration of the drift layer.