Display substrate and method of fabricating the same

A method of fabricating a display substrate comprising:

• forming a semiconductor layer and a data interconnection layer on a substrate;
• forming a semiconductor layer pattern and a data interconnection pattern by etching the semiconductor layer and the data interconnection layer so that an end portion of the semiconductor layer pattern is protruded in one direction beyond an end portion of the data interconnection pattern;
• forming a protection layer and a sacrificial layer on the substrate;
• forming contact holes so that at least a portion of an upper surface of the semiconductor layer pattern and at least a portion of an upper surface of the data interconnection pattern are exposed by etching the protection layer using an etching selection ratio of the protection layer and the semiconductor layer pattern in which the etch rate of the protection layer is greater than the etch rate of the semiconductor layer pattern;
• and
• forming contact electrodes in the contact holes.

A method of fabricating a display substrate comprising:

• sequentially forming a semiconductor layer and a data interconnection layer that comprises first, second and third electrode layers on a substrate;
• forming a semiconductor layer pattern and a data interconnection pattern that comprises first, second and third electrode layer patterns by etching the semiconductor layer and the data interconnection layer so that an end portion of the semiconductor layer pattern protrudes in one direction beyond an end portion of the data interconnection pattern;
• forming a protection layer and a sacrificial layer on the substrate;
• forming a first photoresist pattern with a first thickness and a second photoresist pattern with a second thickness that is smaller than the first thickness on the protection layer and the sacrificial layer;
• forming contact holes so that at least a portion of an upper surface of the semiconductor layer pattern and at least a portion of an upper surface of the data interconnection pattern are exposed by etching the protection layer and the sacrificial layer in an etching selection ratio in which the etch rate of the protection layer is greater than the etch rate of the semiconductor layer using the first and second photoresist patterns as a mask;
• forming a third photoresist pattern by etching back the first and second photoresist patterns;
• forming an undercut by etching an edge portion of the sacrificial layer underneath the third photoresist pattern;
• forming a conduction layer on an upper part of the third photoresist pattern and on an upper surface of the exposed semiconductor layer pattern so that the conduction layer is in contact with the first or third electrode layer pattern;
• and
• lifting off the third photoresist pattern.