Data processing apparatus
AssigneeFuji Xerox Co., Ltd.
InventorsTakao NAITO, Kazuo YAMADA
Life of this patent
Estimating the term…
Abstract
Source code to be processed is analyzed and configuration data in implementing in accordance with each of plural implementation systems is created and is stored in a local memory of a DRP incorporating system. When execution of target processing is started, the implementation system determination processing calculates estimated processing time when the configuration of each of the implementation systems is adopted and determines the optimum one of the implementation systems based on a combination of the estimated processing time and the circuit scale of the configuration.
Claims3
A data processing apparatus comprising:
- an extraction section that extracts a plurality of types of preprocessing in asynchronous relationship with each other and post processing for inputting the processing result of each preprocessing from implementation target processing;
- an implementation section that has as implementation systems for implementing the implementation target processing using a reconfigurable circuit, a plurality of implementation systems including
- (1) a first implementation system for (i) reconfiguring prestage circuits each for each of the plurality of types of preprocessing in order on the reconfigurable circuit, (ii) causing each reconfigured prestage circuit to execute corresponding preprocessing, (iii) storing the processing result of each prestage circuit in memory, (iv) after completion of the processing of each prestage circuit, reconfiguring a poststage circuit for executing the postprocessing on the reconfigurable circuit, (v) inputting the processing result of each prestage circuit stored in the memory into the reconfigured poststage circuit, and causing the circuit to execute processing and
- (2) a second implementation system for reconfiguring each prestage circuit, the poststage circuit, and synchronizing circuit for synchronizing when the processing result of each prestage circuit is input to the poststage circuit on the reconfigurable circuit at the same time, and operating them,
- the implementation section that implements the implementation target processing using the reconfigurable circuit in a selected one of the implementation systems;
- and
- a control section that determines which of the implementation systems is to be adopted based on an estimation value of time required for processing data of a specified data amount when each of the implementation systems is adopted and a circuit scale of the circuits reconfigured at the same time on the reconfigurable circuit in the implementation system,
- the control section that commands the implementation section to implement in the determined implementation system.
Dependencies are inferred from the claim text.