Instruction fetch apparatus and processor

A processor comprising:

• a detection state setting section configured to set the execution state of a program of which an instruction prefetch timing is to be detected;
• a program execution state generation section configured to generate the current execution state of said program;
• an instruction prefetch timing detection section configured to detect said instruction prefetch timing in the case of a match between the current execution state of said program and the set execution state thereof upon comparison therebetween;
• an instruction prefetch section configured to prefetch the next instruction upon detection of said instruction prefetch timing;
• and
• an instruction execution section configured to execute the instruction acquired through the instruction prefetch.

An instruction fetch apparatus comprising:

• detection state setting means for setting the execution state of a program of which an instruction prefetch timing is to be detected;
• program execution state generation means for generating the current execution state of said program;
• instruction prefetch timing detection means for detecting said instruction prefetch timing in the case of a match between the current execution state of said program and the set execution state thereof upon comparison therebetween;
• and
• instruction prefetch means for prefetching the next instruction upon detection of said instruction prefetch timing.