Bounding box prefetcher with reduced warm-up penalty on memory block crossings

A method for prefetching data into a cache memory of a microprocessor, the method comprising:

• detecting a pattern of memory accesses within a first memory block and prefetching into the cache memory cache lines from the first memory block based on the pattern;
• observing a new memory access request to a second memory block;
• determining that the first memory block is virtually adjacent to the second memory block and that the pattern, when continued from the first memory block to the second memory block, predicts an access to a cache line implicated by the new request within the second memory block;
• and
• prefetching into the cache memory cache lines from the second memory block based on the pattern, in response to said determining.

A computer program product encoded in at least one computer readable medium for use with a computing device, the computer program product comprising:

• computer readable program code embodied in said medium, for specifying a microprocessor, the computer readable program code comprising:
• first program code for specifying a cache memory;
• and
• second program code for specifying a data prefetcher, configured to:
• detect a pattern of memory accesses within a first memory block and prefetch into the cache memory cache lines from the first memory block based on the pattern;
• observe a new memory access request to a second memory block;
• determine that the first memory block is virtually adjacent to the second memory block and that the pattern, when continued from the first memory block to the second memory block, predicts an access to a cache line implicated by the new request within the second memory block;
• and
• responsively prefetch into the cache memory cache lines from the second memory block based on the pattern.