Memory system, personal computer, and method of controlling the memory system
AssigneeKabushiki Kaisha Toshiba
InventorTakayuki ABE
Life of this patent
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AssigneeKabushiki Kaisha Toshiba
InventorTakayuki ABE
Estimating the term…
According to one embodiment, a memory system includes: a nonvolatile semiconductor memory including a plurality of normal blocks and at least one dummy block, each of the normal blocks being a unit of data erasing; a writing control unit that rewrites the dummy block the number of times equal to or larger than a maximum number of times among the numbers of times of rewriting of the normal blocks; a monitor unit that monitors a data erasing time or a data writing time of the dummy block; and a wear-leveling control unit that averages the numbers of times of rewriting of the normal blocks. The memory system determines, based on a monitor result of the monitor unit, possibility of continuation of the rewriting of the normal blocks.
A memory system comprising:
A memory system comprising:
A method of controlling a memory system including a nonvolatile semiconductor memory having a plurality of normal blocks and at least one dummy block, each of the normal blocks being a unit of data erasing, the method comprising:
Dependencies are inferred from the claim text.